module firstDemo(clk,rst_n,led);
	input clk,rst_n;
	
	output reg [2:0]led;
	
	parameter Tls = 50_000_000;
	
	reg[25:0] count;
	reg[1:0] state;
	localparam 
	s0=2'b00,s1=2'b01,s2=2'b10;
	
	always @ (posedge clk or negedge rst_n)
		begin
			if(!rst_n)
				begin
					count <= 0;
					led <= 3'b111;
					state <= s0;
				end
			else
				begin
					case (state)
					s0: begin
							if(count < Tls - 1)
								begin
									count <= count+1;
									led <= 3'b011;
									state <= s0;
								end
							else
								begin
									count <= 0;
									state <=s1;
								end
						 end
					s1: begin
							if(count < Tls - 1)
								begin
									count <= count+1;
									led <= 3'b101;
									state <= s1;
								end
							else
								begin
									count <= 0;
									state <=s2;
								end
						end
					s2: begin
							if(count < Tls - 1)
								begin
									count <= count+1;
									led <= 3'b110;
									state <= s2;
								end
							else
								begin
									count <= 0;
									state <= s0;
								end
						end
					default: state <= s0;
				endcase
		end
	end

endmodule
